This invention relates, in general, to semiconductor memory devices and more particularly, to electrically alterable, nonvolatile floating gate memory devices.
The microprocessor based systems, as well as the related arts, have long required electrically alterable read only memory (EAROM) elements that were nonvolatile and many such devices have, to some extent, filled this need. However, as the computer arts have become more complex in nature and have required high speeds and greater capacity there now exists the need for a high density memory device that may be easily programmed or "written" and, as the occasion arises, to reprogram ("erase" and "rewrite") the device in the field. To this end, devices are presently available to the design engineers that exhibit nonvolatile characteristics but, as will be discussed, they have inherent shortcomings that are overcome by the subject invention.
One such device resides in the family of Floating Gate Avalanche Metal Oxide Semiconductor (FAMOS) devices. The advantage of this type of device resides in the fact that it is independent of any outside current to maintain the stored information in the event power is lost or interrupted. Since these devices are independent of any outside power there is also no need to refresh the device which feature results in a significant savings in power.
The floating gate family of devices usually has source and drain regions of a given conductivity type, formed in a substrate of the opposite conductivity type, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is constructed by first applying a thin insulating layer followed by a conductive layer (the floating gate) which is usually followed by a second insulating layer in order to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (usually referred to as the control gate) is formed over the second insulating layer (in the region of the floating gate) to complete the gate structure. Such devices are exemplified in U.S. Pat. No. 3,500,142 which issued to D. Khang on Mar. 10, 1970 and U.S. Pat. No. 3,660,819 which issued to D. Frohman-Bentchkowsky on May 2, 1972.
The major drawback of these prior art devices resides in the fact that high fields are required to produce the necessary avalanche breakdown in order for charge to be placed on the floating gate. Further, to erase charge placed on the floating gate, the entire device must be provided with a transparent window so that the chip may be flooded with energy in the ultra violet or x-ray portion of the spectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the device then requiring that the entire chip be completely reprogrammed. Further, the erasing step required an extremely long period of exposure time, of the order of about 30 to 45 minutes, with the device or chip removed from the equipment.
In recent years, the art has progressed to the point where nonvolatile, floating gate read only memory devices have been produced which are electrically alterable. One such memory cell has been described in detail in an article entitled "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage" by W. S. Johnson, et al., ELECTRONICS, Feb. 28, 1980, pp. 113-117. In this article, the authors describe a "Floating-Gate Tunnel Oxide" structure wherein a cell using a polycrystalline silicon (polysilicon) floating gate structure has its gate member charged with electrons (or holes) through a thin oxide layer positioned between the floating gate and the substrate by means of the Fowler-Nordheim tunneling mechanism. An elevation view of a typical device is described, and shown in FIG. 1 of the article, wherein the floating gate member represents the first polysilicon level. By using this type of structure (a structure wherein the first level polysilicon represents the floating gate since it is closest to the substrate, and is covered by a second polysilicon level) an excessively high floating gate-to-substrate capacitance is produced. However, acceptably low "write" and "erase" operations can only be achieved when most of the applied voltage appears across the tunnel region which requires that the floating gate-to-control gate (second polysilicon level) capacitance be larger than the floating gate-to-substrate capacitance. Further, to achieve the required distribution of capacitance to produce the acceptable "write" and "erase" characteristics, the prior art has resorted to extending both the first and second polysilicon levels over the adjacent field oxide to obtain the additional capacitance. The net result is an undesirably large cell.
In one recent application, filed in the U.S. Patent and Trademark Office on Oct. 18, 1982, Ser. No. 437,271 entitled "AN ELECTRICALLY ALTERABLE, NONVOLATILE FLOATING GATE MEMORY DEVICE," and assigned to the same assignee as the subject application, and now U.S. Pat. No. 4,558,339, there is described a novel configuration of a floating gate memory device wherein the floating gate is a second level polysilicon rather than the traditional first level polysilicon. This is done in order that the second level polysilicon floating gate be provided with a shield. The first level polysilicon is provided with an aperture and the second level floating gate is made to extend through the aperture so that only a relatively small area of the second level floating gate is coupled to the substrate. By providing such a structure it was found that the otherwise high floating gate-to-substrate capacitance was reduced. These ends are accomplished by providing a dual section portion, extending from the source region, to create an auxiliary channel region for "erasing" and "writing" into the resultant cell.
In another recent application entitled "AN ELECTRICALLY ALTERABLE, NONVOLATILE FLOATING GATE MEMORY DEVICE," filed by the subject inventors in the U.S. Patent and Trademark Office on Dec. 10, 1982, Ser. No. 448,690, and assigned to the same assignee as the subject application, and now U.S. Pat. No. 4,513,397 we describe an electrically alterable, nonvolatile floating gate memory device wherein the floating gate portion is the second level polysilicon. In our co-pending application, we are able to reduce the area previously occupied by each device by coupling the floating gate to the substrate at the portion of the channel region that conduction takes place. The coupling takes place through a self-aligned, rectangularly shaped aperture in the first level polysilicon layer. The aperture has its short sides parallel to the sides of the first level polysilicon layer, but spaced therefrom to allow for mask alignment tolerances. The optimum dimension of the aperture was found to be about 5 microns long and about 2 microns wide with a 2 micron tolerance between each end of the aperture and the adjacent side of the first level polysilicon. This then dictated that the side-to-side dimension of the first and third level polysilicon layers be about 9-10 microns while the aperture is about 5 microns long. In practice, it was found that each device required a minimum active area of about 210 square micrometers (micron) to provide reliable devices consistent with good manufacturing techniques in order to produce consistently high yields. By removing the need to maintain certain mask tolerances, we find that the active area can be reduced by about 30%, thus making space available for additional devices in the same chip area.